1. Technical Field
The present invention generally relates to semiconductor devices. More particularly, the present invention relates to the integration of micro-electromechanical systems (MEMS) or nano-electromechanical systems (NEMS) with metal-oxide-semiconductor (MOS) devices and processes.
2. Description of the Related Art
The ever increasing demand of small, portable multifunctional electronic devices has led to the continued proliferation of smart phones, personal computing devices, personal audio devices (e.g., MP3 players), as well as biomedical and security devices. Such devices are expected to support and perform a greater number of increasingly complex and sophisticated functions while consuming less and less power. Such electronic devices rely on limited power sources (e.g., batteries and/or alternative energy harvesting systems) while providing ever-increasing processing capabilities and storage capacity.
In an attempt to reduce overall integrated circuit (IC) power consumption, various power gating techniques have been introduced to disable current flow to IC devices and circuitry when not in use, for example, when the device is in a non-operation mode so as to reduce standby consumed power. One common power gating technique includes using MOS transistors to switch connections to power or ground networks ON and OFF. The power gating technique can be understood with reference to FIG. 1, which shows a MOS power gate 102 coupled to a circuit block 104, where the MOS power gate 102 controls the power supplied to the circuit block 104 from a voltage supply (VDD) by way of the gate control signal at an input of the MOS power gate 102. For example, in some cases, when the gate control signal is low (logic 0), the MOS power gate 102 is ON, and a virtual VDD coupled to the circuit block 104 is approximately equal to VDD. Alternatively, in some cases, when the gate control signal is high (logic 1), the MOS power gate 102 is OFF, and the virtual VDD is approximately zero, thus effectively turning off of the power supplied to the circuit block 104. While the example of FIG. 1 shows the MOS power gate 102 connected between the circuit block 104 and the power network (VDD), the MOS power gate 102 could also be coupled between the circuit block 104 and a ground connection (VSS). Power gating of electronic devices becomes particularly important for devices that rely on limited power sources, spend a majority of their time in an OFF state or sleep mode (i.e., a non-operation mode), and which only operate on periodic and/or event-driven schedules, such as for example, motion-detecting security systems and biological implants which may only infrequently collect/analyze data or provide a drug release, among others.
The most common way to implement power gates has been through the use of MOS transistors, as illustrated in FIG. 1. However, as the minimum feature size of MOS devices has continuously decreased in an effort to meet stringent demands on device performance and power consumption, the OFF state leakage current has increased, and is rapidly approaching ON state current levels. This increased OFF state leakage, together with the fact that many electronic devices are spending a majority of their time in a non-operation mode, results in a dominant source of power consumption being the OFF state leakage occurring while the device is in a non-operation mode. Moreover, the voltage drop present in MOS devices while in an ON state can significantly degrade device performance, particularly in aggressively scaled and embedded IC devices.